Analog-to-Digital Converters (ADCs) typically convert an analog input voltage into a digital output code. In order to do this, most ADCs compare the input voltage to a reference voltage using a device such as a comparator. A 1-bit ADC uses a single comparator and compares the input voltage to the reference voltage. The ADC outputs a “1” if the input is higher than the reference voltage, and a “0” if the input voltage is lower than the reference voltage. Multi-bit ADCs are more complex, and generate multi-bit output codes. One such multi-bit ADC is a successive approximation register (SAR) ADC. A SAR ADC operates by generating a digital approximation of the analog input voltage. It does this bit-by-bit, starting with the highest bit (the most significant bit, or MSB) and moving down to the lowest bit (the least significant bit, or LSB). To do this, it uses a digital-to-analog converter (DAC) which generates an analog voltage to compare with the input voltage using a comparator. It is common for SAR ADCs to use capacitive DACs, however, other types of DAC are used in some SAR ADCs. The DAC requires a reference voltage in order to generate a suitable analog voltage for comparison with the input voltage.
The voltage reference is typically supplied by a voltage reference circuit. In the case of SAR ADCs, the voltage reference circuit provides charge to the ADC using one or more capacitors. For example, a typical voltage reference circuit for a SAR ADC includes a reference buffer connected to a decoupling capacitor. The reference buffer may or may not be provided on the same chip as the ADC. However, the decoupling capacitor is required to be large (in the order of 10 uF), and is therefore provided off-chip. The decoupling capacitor is required to be large because it needs to provide enough charge for a complete conversion, which includes multiple bit trials. The capacitor needs to be large enough such that the accuracy of later bit trials are not degraded as the charge of the decoupling capacitor is reduced. However, a large off-chip capacitor is expensive and utilises valuable area on the printed circuit board (PCB). Furthermore, a large decoupling capacitor means that the output impedance of the circuit is required to be low, which in turn makes design of the reference buffer challenging.
In addition to the above, a key requirement of the voltage reference circuit is that reference value does not drop too much as the ADC draws charge during a conversion phase. The reference buffer needs to charge the off-chip capacitor back to the reference charge before the next conversion phase starts. The greater the drop in charge, the more work the reference buffer has to do.